This invention relates to a circuit arrangement for processing electrical signals in the form of sampled analogue currents, the circuit arrangement comprising a first current memory cell having a current input for receiving an input analogue current and a current output for producing a stored analogue current and comprising a first field effect transistor having its drain and gate electrodes coupled via a first switch which is controlled by means of a clock signal such that it is closed during a first portion of a clock period, means for coupling the current input to the drain electrode of the first transistor during the first portion of the clock period, means for coupling the current output to the drain electrode of the first transistor during a second portion of the clock period, and means for feeding a first bias current to the drain electrode of the first transistor, a second current memory cell connected in cascade with said first current memory cell, said second current memory cell having a current input for receiving an input analogue current and a current output for producing a stored analogue current and comprising a second field effect transistor having its drain and gate electrodes coupled via a first switch which is controlled by means of a clock signal such that it is closed during a second portion of the clock period, means for coupling the current input to the drain electrode of the second transistor during the second portion of the clock period, means for coupling the current output to the drain electrode of the transistor during the first portion of the clock period, and means for feeding a second bias current to the drain electrode of the transistor.
A class of analogue signal processing arrangements which manipulates units of currents has become known as switched current circuits. These arrangements are constructed from current amplifying and summing circuits and current memory circuits. The current memory circuits or cells may comprise in their simplest form a field effect transistor having a switch connected between its gate and drain electrodes. An input current is fed to the drain electrode when the switch is closed and causes the gate-source capacitance to be charged. When the switch is opened the voltage at the gate electrode is maintained by the charge on the gate-source capacitance and this causes the transistor to reproduce the same current as was fed to it when the switch was closed. Normally two further switches are provided, one closed in synchronism with the first switch to apply an input current to the transistor and the other closed during a second period to provide a means for deriving an output current, the output current being a replica of the input current and being produced during a later portion of the clock period or during a portion of a later clock period. Thus the current memory cell can act as an analogue signal delay circuit with a unit delay of half a clock period being easily realisable.
This basic current memory cell has certain limitations in its analogue performance due to non-ideal MOS transistor performance, in particular non-zero output conductance, finite bandwidth, and switch charge injection.
The reduction of switch charge injection in dynamic current mirrors which use a cell having the same form as used in switched current circuits as the current memory cell is proposed in a paper by G. Wegmann and E. A. Vittoz entitled "Analysis and Improvements of Accurate Dynamic Current Mirrors" published in IEEE Journal of Solid State Circuits, Vol. 25, No. 3, June 1990, pages 699-706. The authors adopt two measures, the provision of symmetrical dummy switches and the control of the amplitude of the clock signal controlling the switches to cause it to adopt the minimum level required to switch the current applied to the cell. Both of these measures will reduce the magnitude of the error current produced as a result of charge injection when the switches are operated by reducing the magnitude of the charge injection.